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74AC16244 * 74ACT16244 16-Bit Buffer/Line Driver with 3-STATE Outputs
August 1999 Revised May 2005
74AC16244 * 74ACT16244 16-Bit Buffer/Line Driver with 3-STATE Outputs
General Description
The AC16244 and ACT16244 contain sixteen non-inverting buffers with 3-STATE outputs designed to be employed as a memory and address driver, clock driver, or bus oriented transmitter/receiver. The device is nibble controlled. Each nibble has separate 3-STATE control inputs which can be shorted together for full 16-bit operation.
Features
s Separate control logic for each byte and nibble s 16-bit version of the AC244/ACT244 s Outputs source/sink 24 mA s ACT16244 has TTL-compatible inputs
Ordering Code:
Order Number 74AC16244SSC 74ACT16244SSC 74ACT16244MTD Package Number MS48A MS48A MTD48 Package Description 48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide 48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Device also available in Tape and Reel. Specify by appending suffix letter "X" to the ordering code.
Logic Symbol
Connection Diagram
Pin Descriptions
Pin Names OEn I0 - I15 O0 - 015 Description Output Enable Input (Active LOW) Inputs Outputs
FACT is a trademark of Fairchild Semiconductor Corporation.
(c) 2005 Fairchild Semiconductor Corporation
DS500295
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74AC16244 * 74ACT16244
Functional Description
The AC16244 and ACT16244 contain sixteen non-inverting buffers with 3-STATE standard outputs. The device is nibble (4 bits) controlled with each nibble functioning identically, but independent of the other. The control pins can be shorted together to obtain full 16-bit operation. The 3-STATE outputs are controlled by an Output Enable (OEn) input for each nibble. When OEn is LOW, the outputs are in 2-state mode. When OEn is HIGH, the outputs are in the high impedance mode, but this does not interfere with entering new data into the inputs.
Truth Tables
Inputs OE1 L L H I0-I3 L H X Outputs O0-O3 L H Z OE2 L L H Inputs I4-I7 L H X Outputs O4-O7 L H Z
Inputs OE3 L L H
L LOW Voltage Level H HIGH Voltage Level
Outputs I8-I11 L H X O8-O11 L H Z
X Z
Inputs OE4 L L H
Immaterial High Impedance
Outputs I12-I15 L H X O12-O15 L H Z
Logic Diagram
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74AC16244 * 74ACT16244
Absolute Maximum Ratings(Note 1)
Supply Voltage (VCC) DC Input Diode Current (IIK) VI VI VO
0.5V to 7.0V 20 mA 20 mA
Recommended Operating Conditions
Supply Voltage (VCC) AC ACT Input Voltage (VI) Output Voltage (VO) Operating Temperature (TA) Minimum Input Edge Rate ('V/'t) AC Devices VIN from 30% to 70% VCC @ 3.3V, 4.5V, 5.5V Minimum Input Edge Rate ('V/'t) ACT Devices VIN from 0.8V to 2.0V VCC @ 4.5V, 5.5V 125 mV/ns
Note 1: Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specifications should be met, without exception to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. Fairchild does not recommend operation of FACT circuits outside databook specifications.
0.5V VCC 0.5V 0.5V VCC 0.5V
2.0V to 6.0V 4.5V to 5.5V 0V to VCC 0V to VCC
DC Output Diode Current (IOK)
20 mA 20 mA VO 0.5V to VCC 0.5V DC Output Voltage (VO) DC Output Source/Sink Current (IO) r50 mA
DC VCC or Ground Current per Output Pin Junction Temperature Storage Temperature
40qC to 85qC
r50 mA 140qC 65qC to 150qC
125 mV/ns
DC Electrical Characteristics for AC
Symbol VIH Parameter Minimum HIGH Input Voltage VCC (V) 3.0 4.5 5.5 VIL Maximum LOW Input Voltage 3.0 4.5 5.5 VOH Minimum HIGH Output Voltage 3.0 4.5 5.5 3.0 4.5 5.5 VOL Maximum LOW Output Voltage 3.0 4.5 5.5 3.0 4.5 5.5 IOZ Maximum 3-STATE Leakage Current 5.5 0.002 0.001 0.001 TA Typ 1.5 2.25 2.75 1.5 2.25 2.75 2.99 4.49 5.49 2.1 3.15 3.85 0.9 1.35 1.65 2.9 4.4 5.4 2.56 3.86 4.86 0.1 0.1 0.1 0.36 0.36 0.36 0.50
25qC
TA
40qC to 85qC
2.1 3.15 3.85 0.9 1.35 1.65 2.9 4.4 5.4 2.46 3.76 4.76 0.1 0.1 0.1 0.44 0.44 0.44
Guaranteed Limits
Units VOUT V
Conditions 0.1V
or VCC 0.1V VOUT 0.1V
V
or VCC 0.1V
V
IOUT IOH
50 PA
-12 mA
V
IOH IOH
24 mA 24 mA (Note 2)
50 PA 12 mA 24 mA 24 mA (Note 2) VIL, VIH VCC, GND VCC, GND VCC, GND VCC or GND 1.65V Max 3.85V Min
V
IOUT IOL
V
IOL IOL
r 5.0
PA
VI (OE) VI VO
IIN ICC IOLD IOHD
Maximum Input Leakage Current (Note 3) Max Quiescent Supply Current (Note 3) Minimum Dynamic Output Current (Note 4)
5.5 5.5 5.5 5.5
r 0.1
8.0
r 1.0
80.0 75
PA PA
mA mA
VI VIN
VOLD VOHD
75
Note 2: All outputs loaded; thresholds associated with output under test. Note 3: IIN and ICC @ 3.0V are guaranteed to be less than or equal to the respective limit @ 5.5V VCC. Note 4: Maximum test duration 2.0 millisecond; one output loaded at a time.
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74AC16244 * 74ACT16244
DC Electrical Characteristics for ACT
Symbol VIH VIL VOH Parameter Minimum HIGH Input Voltage Maximum LOW Input Voltage Minimum HIGH Output Voltage VCC (V) 4.5 5.5 4.5 5.5 4.5 5.5 4.5 5.5 VOL Maximum LOW Output Voltage 4.5 5.5 4.5 5.5 IOZ IIN ICCT ICC IOLD IOHD Maximum 3-STATE Leakage Current Maximum Input Leakage Current Maximum ICC/Input Max Quiescent Supply Current Minimum Dynamic Output Current (Note 6) 5.5 5.5 5.5 5.5 5.5 0.6 8.0 0.001 0.001 TA Typ 1.5 1.5 1.5 1.5 4.49 5.49 2.0 2.0 0.8 0.8 4.4 5.4 3.86 4.86 0.1 0.1 0.36 0.36
25qC
TA
40qC to 85qC
2.0 2.0 0.8 0.8 4.4 5.4 3.76 4.76 0.1 0.1 0.44 0.44
Guaranteed Limits
Units V V V VOUT VOUT
Conditions 0.1V 0.1V
or VCC 0.1V or VCC 0.1V IOUT VIN
50 PA
VIL or VIH
V
IOH IOH
24 mA 24 mA (Note 5)
50 PA VIL or VIH 24 mA 24 mA (Note 5) VIL, VIH VCC, GND VCC, GND VCC 2.1V VCC or GND 1.65V Max 3.85V Min
V
IOUT VIN
V
IOH IOH VI VO VI VI VIN VOLD VOHD
r 0.5 r 0.1
r 5.0 r 1.0
1.5 80.0 75
PA PA
mA
PA
mA mA
75
Note 5: All outputs loaded; thresholds associated with output under test. Note 6: Maximum test duration 2.0 millisecond; one output loaded at a time.
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74AC16244 * 74ACT16244
AC Electrical Characteristics for AC
VCC Symbol tPLH tPHL tPZH tPZL tPHZ tPLZ Parameter Propagation Delay Data to Output Propagation Delay Data to Output Output Enable Time Output Enable Time Output Disable Time Output Disable Time (V) (Note 7) 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0
Note 7: Voltage Range 5.0 is 5.0V r 0.5V. Voltage Range 3.3 is 3.3V r 0.3V.
TA CL Min 2.0 1.6 2.4 2.0 2.2 1.7 2.9 2.2 3.1 1.9 2.4 1.7
25qC
50 pF Typ 6.3 4.6 5.7 4.3 6.2 4.6 6.4 4.7 5.5 3.9 4.7 3.6 Max 9.4 6.5 10.7 7.0 10 6.7 13.0 8.1 8.4 7.8 8.1 7.2
TA
40qC to 85qC
CL 50 pF Max 10.8 7.1 11.8 7.9 11.5 7.5 14.6 9.0 9.1 8.4 8.8 7.6 ns ns ns ns ns ns Units
Min 2.0 1.6 2.4 2.0 2.2 1.7 2.9 2.2 3.1 1.9 2.4 1.7
AC Electrical Characteristics for ACT
VCC Symbol Parameter (V) (Note 8) tPLH tPHL tPZH tPZL tPHZ tPLZ Propagation Delay Data to Output Output Enable Time Output Disable Time 5.0 5.0 5.0 Min 3.0 2.5 2.5 2.7 2.3 2.0 TA CL
25qC
50 pF Typ 5.2 4.8 5.0 4.6 5.0 4.6 Max 7.3 6.8 7.4 7.5 7.9 7.4
TA
40qC to 85qC
CL 50 pF Max 7.8 7.3 7.9 8.0 8.2 7.9 ns ns ns Units
Min 3.0 2.5 2.5 2.7 2.3 2.0
Note 8: Voltage Range 5.0 is 5.0V r 0.5V.
Capacitance
Symbol CIN COUT CPD Input Pin Capacitance Output Pin Capacitance Power Dissipation Capacitance 74AC16244 74ACT16244 Parameter Typ 4.5 12 35 30 Units pF pF pF VCC VCC VCC 5.0V 5.0V 5.0V Conditions
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74AC16244 * 74ACT16244
Physical Dimensions inches (millimeters) unless otherwise noted
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide Package Number MS48A
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74AC16244 * 74ACT16244 16-Bit Buffer/Line Driver with 3-STATE Outputs
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Package Number MTD48
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 7 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com
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